The present invention relates to switching regulator circuits. More particularly, the present invention relates to circuits and methods for maintaining constant amounts of slope compensation in switching regulators regardless of switching frequency of the regulators.
The purpose of a voltage regulator is to provide a predetermined and substantially constant output voltage to a load from a voltage source which may be poorly-specified or fluctuating. Two types of regulators are commonly used to provide this function; a linear regulator and a switching regulator. In a typical linear regulator, the output voltage is regulated by controlling the flow of current through a pass element from the voltage source to the load.
In switching voltage regulators, however, the flow of current from the voltage source to the load is not steady, but is rather in the form of discrete current pulses. To create the discrete current pulses, switching regulators usually employ a switch (such as a power transistor) that is coupled either in series or parallel with the load. The current pulses are then converted into a steady load current with an inductive storage element.
By controlling the duty cycle of this switchxe2x80x94i.e., the percentage of time that the switch is ON relative to the total period of the switching cyclexe2x80x94the switching voltage regulator can regulate the load voltage. In current-mode switching voltage regulatorsxe2x80x94i.e., a switching regulator that is controlled by a current-derived signal in the regulatorxe2x80x94there is an inherent instability when the duty cycle exceeds 50%)xe2x80x94i.e., when the switch is ON for more than 50% of a given switching period. Stability is often maintained in such current-mode switching regulators by adjusting the current-derived signal used to control the regulator with a slope compensation signal which compensates for the instability present at higher duty cycles.
One method of producing such a slope compensation signal is to use a portion of an oscillator signal as the compensation signal. The oscillator signal may be, for example, a ramp signal that is used to generate a clock signal that controls the switching of the regulator. The slope compensation signal can be applied by either adding the ramp signal to the current derived signal, or by subtracting it from a control signal. By deriving the slope compensation signal from a signal that oscillates the switch of the regulator, the slope compensation signal is advantageously synchronized with the switching of the regulator.
FIG. 1 shows an oscillator circuit 100 that may be used to set the switching frequency and to generate slope compensation.
FIG. 2 is a timing diagram which illustrates the operation of the circuit in FIG. 1. FIG. 2 indicates that the oscillator controls the switching frequency of the switching regulator as follows: The oscillator controls the frequency of the switching regulator by charging capacitor 110 to a reference voltage through a controllable current source 120. The voltage of capacitor 110 is shown as the voltage at node A at line 1 of FIG. 2.
The voltage on capacitor 110 provides a dynamic indication of the duty cycle of circuit 100. For example, when the voltage is 0V, circuit 100 is at the beginning of its duty cycle and when the voltage on the capacitor is at VREF, circuit 100 is near the end of its duty cycle. This is important to slope compensation because duty cycle information is crucial to providing the proper amount of slope compensation. Thus, the voltage on capacitor 110 can be used to govern the amount of slope compensation.
This voltage at node A causes comparator 130 to trip when the capacitor voltage rise to VREF. The output of comparator 130, which provides the output signal to the control logic of the switching regulator, to node A is shown at line 3 of FIG. 2. When comparator 130 trips, this commences the ON-portion of the duty cycle of the switching regulator. When latch 140 changes its output such that switch 150 closes, capacitor 110 discharges rapidly. Line 2 in FIG. 2, indicated by xcfx86A in FIGS. 1 and 2, shows the activity of the output of latch 140. When the voltage at node A falls to VR2 level, comparator 160 trips. This resets latch 140 and switch 150 turns OFF. At this point, capacitor 110 begins to charge and the cycle is repeated.
FIG. 3 is a circuit 300 which utilizes the capacitor 110""s voltage to generate slope compensation current. Resistor string 310, 320, 330 and 340 sets the different points in the duty cycle at which the rate of change in scope compensation is determined.
FIG. 4 shows three break points at which resistor string 310-340 obtains different levels of slope compensation. The first break point is normally set at about 40% duty cycle (preferably below 50% duty cycle). Transistor 350 typically turns on at the first break point. Transistor 360 typically turns on at the second break point and adds more current to the slope compensation signal. Transistor 370 typically turns on at the third break point and adds even more current. Resistors 372, 374 and 376 are required for operation of the circuit.
In particular implementations, such as communications circuitry, it is advantageous to synchronize the operation of the regulator to a higher frequency by using an external clock. One way to force the regulator to a higher frequency is by forcing the oscillator""s capacitor to discharge prematurely. However, by doing that, the circuit loses crucial duty cycle information. Without proper duty cycle information, insufficient slope compensation can result.
One possible solution for this problem is solved by adding circuitry to detect the presence of an external clock. Once the external clock is detected, the slope compensation is then increased by a fixed factor to account for the maximum synchronizable frequency. One problem with this approach is that if the regulator is synchronized just slightly above the normal operating frequency, overcompensation results. The result of this compensation causes the maximum output current to be reduced by the amount of the overcompensation.
Another approach to synchronize without reducing the effectiveness of the slope compensation is to implement a phase lock loop (PLL) together with the regulator on the chip. The PLL ensures the voltage on the oscillator""s capacitor always reaches the trip voltage as long as the external clock is within its capture rangexe2x80x94i.e., the range in which the PLL can track the frequency. Thus, the duty cycle information on the oscillator capacitor is retained. However, this approach requires an additional pin on the chip because the PLL loop filter components are typically too large to implement on the chip.
Therefore, it would be desirable to provide a circuit that maintains slope compensation while synchronizing the operation of the regulator to an external clock frequency.
It would also be desirable to provide a circuit that maintain slope compensation over substantially the entire range of operation of the regulator.
It would also be desirable to provide an integrated circuit that maintains slope compensation with a minimum of additional circuitry.
It is therefore an object of the present invention to provide a circuit that maintains slope compensation while synchronizing the operation of the regulator to an external clock frequency.
It is another an object of the present invention to provide a circuit that maintains slope compensation over substantially the entire range of operation of the regulator.
It is a further an object of the present invention to provide an integrated circuit that maintains slope compensation with a minimum of additional circuitry.
These and other objects of the present invention are accomplished by providing an oscillator circuit that includes a capacitor that provides a first voltage, a window comparator circuit coupled to the capacitor that provides a first output signal and a second output signal based on the first voltage, a counter circuit that provides a control signal based on the first output signal and the second output signal and a controllable current source that controls the first voltage based on the control signal.
A preferable method according to the invention of synchronizing a oscillating capacitor to an external clock frequency while substantially maintaining a constant peak voltage of the oscillating capacitor includes charging and discharging a capacitor at the external clock frequency, comparing the peak to a first reference voltage to provide a first output signal, comparing the peak to a second reference voltage to provide a second output signal, producing a control signal by one of a group consisting of 1) counting up, 2) counting down, and 3) remaining the same, based on the first and second output signals, and adjusting the peak based on the control signal.